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The January 2025 foundry due-diligence rule allows reliance on an attestation that the aggregated approximated transistor count of the final packaged IC is below 30 billion transistors, or, for ICs without high bandwidth memory, below 35 billion in 2027 and 40 billion later, as one route around the new licence requirement, alongside lists of approved IC designers and OSAT companies. Copy claim link
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Supporting evidence: primary · 1 source
Provision Threshold or trigger · provision ID ch-bis-foundry-dd-2025-transistor-attestation Subject version As published in the Federal Register (16 January 2025), 90 FR 5298 · Published 2025-01-16 · Effective 2025-01-16 Date 2025-01-16 · publication Scope and limits A paraphrase of a conditional provision with several branches; the exact years for the 40 billion threshold are cut off in the quotation and should be read in the rule. It does not show which chips or foundries were affected.
The evidence 02 primary source Supports the claim
Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits; Amendments and Clarifications; and Extension of Comment Period (90 FR 5298) ↗ Bureau of Industry and Security, in the Federal Register (govinfo.gov) · 2025-01-16
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Source excerpt “the ‘‘aggregated approximated transistor count’’ of the final packaged IC is below 30 billion transistors, or (b) the final packaged IC does not contain high bandwidth memory (HBM) and that the ‘‘aggregated approximated transistor count’’ of the final packaged IC is below (i) 35 billion transistors” Location in source 90 FR 5305, preamble (PDF p. 8)
How it was read Retrieved directly from the publisher
Machine-checked · 2026-10-30
Source details and check notes Authors Bureau of Industry and Security, U.S. Department of Commerce Version Retrieved for the candidate pack on 2026-10-28 (SHA-256 e1f7ddd6e4fd08d1ee1470bd001d38ca16adb28bb42444640775a63c7bef1026). Federal Register print of Thursday, January 16, 2025, Vol. 90, No. 10, beginning at p. 5298, FR Doc. 2025-00711 (filed 1-15-25). Interim final rule. Retrieved again at admission on 2026-10-30 (SHA-256 e1f7ddd6e4fd08d1ee1470bd001d38ca16adb28bb42444640775a63c7bef1026, the same bytes). Canonical address Open the canonical source ↗ Accessed 2026-10-28 Language English (en) Attribution Bureau of Industry and Security, U.S. Department of Commerce, “Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits; Amendments and Clarifications; and Extension of Comment Period (90 FR 5298)”, 2025-01-16. Reuse No open redistribution licence asserted. Bibliographic metadata, editorial paraphrases and short attributed quotations (at most 50 words each). Recheck terms before wider redistribution. Check notes Candidate pack passage, compute, power and orbit (research/compute-power-orbit). The quotation (46 words) matched the text retrieved for the candidate pack on 2026-10-28 and again at admission on 2026-10-30, in a fresh retrieval whose SHA-256 equals the pack’s. Matching ignored differences of whitespace, case, quotation marks, dashes and Unicode compatibility forms, so the source’s typography can differ. No human editorial review. primary source Supports the claim
Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits; Amendments and Clarifications; and Extension of Comment Period (90 FR 5298) ↗ Bureau of Industry and Security, in the Federal Register (govinfo.gov) · 2025-01-16
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Source excerpt “Approved IC designers (listed in supplement no. 6 to part 740), (ii) Approved ‘‘OSAT’’ companies (listed in supplement no. 7 to part 740)” Location in source 90 FR 5301, preamble (PDF p. 4)
How it was read Retrieved directly from the publisher
Machine-checked · 2026-10-30
Source details and check notes Authors Bureau of Industry and Security, U.S. Department of Commerce Version Retrieved for the candidate pack on 2026-10-28 (SHA-256 e1f7ddd6e4fd08d1ee1470bd001d38ca16adb28bb42444640775a63c7bef1026). Federal Register print of Thursday, January 16, 2025, Vol. 90, No. 10, beginning at p. 5298, FR Doc. 2025-00711 (filed 1-15-25). Interim final rule. Retrieved again at admission on 2026-10-30 (SHA-256 e1f7ddd6e4fd08d1ee1470bd001d38ca16adb28bb42444640775a63c7bef1026, the same bytes). Canonical address Open the canonical source ↗ Accessed 2026-10-28 Language English (en) Attribution Bureau of Industry and Security, U.S. Department of Commerce, “Implementation of Additional Due Diligence Measures for Advanced Computing Integrated Circuits; Amendments and Clarifications; and Extension of Comment Period (90 FR 5298)”, 2025-01-16. Reuse No open redistribution licence asserted. Bibliographic metadata, editorial paraphrases and short attributed quotations (at most 50 words each). Recheck terms before wider redistribution. Check notes Candidate pack passage, compute, power and orbit (research/compute-power-orbit). The quotation (23 words) matched the text retrieved for the candidate pack on 2026-10-28 and again at admission on 2026-10-30, in a fresh retrieval whose SHA-256 equals the pack’s. Matching ignored differences of whitespace, case, quotation marks, dashes and Unicode compatibility forms, so the source’s typography can differ. No human editorial review. Status and meaning Editorial status. Not reviewed by an editor . An exploratory record that no editor has accepted. This status does not say whether a person has read any linked passage. Each evidence record above shows how it was checked.
Relation. An exact framework edition, or another document with an exact expression, states one provision: a capability threshold or risk level and its trigger, a required safeguard or action, a decision authority (who decides, recommends, can overrule or is informed), a stated exception, or another statement of its content, such as a licence term or a prospectus statement. The passage records what the document says, not implementation, compliance or effectiveness. Provisions with the same key align across editions of one family.
Date. Date of publication, as the source gives it.
Record ID cpo-ch-bis-foundry-dd-2025-transistor-attestation